1. Field of the Invention
The present invention relates generally to digital quadrature amplitude modulation filtering techniques. More specifically, the invention relates to an efficient quadrature amplitude modulator with a digital filter implementation that significantly decreases required processing power.
2. Description of the Prior Art
In digital communication technology today, one of the more common methods of packing more data bits within an allocated bandwidth is performed using multilevel systems or M-ary techniques. Since digital transmission is notoriously wasteful of RF bandwidth, regulatory authorities usually require a minimum bit packing. One of the more common techniques combining both amplitude and phase modulation is known as M-ary quadrature amplitude modulation (QAM). QAM modulates two different signals into the same bandwidth. This is accomplished by creating a composite amplitude modulated signal using two carriers of the same frequency. The two carriers are distinguished by having a phase difference of 90 degrees. By convention, the cosine carrier is called the in-phase component and the sine carrier is the quadrature component.
A prior art, all digital architecture 15 for a QAM modulator 17 is shown in FIG. 1. The modulator 17 accepts a digital input 19, where it is converted 21 from a serial bitstream to a parallel configuration for input into an encoder 23. The encoder 23 divides the incoming signal into a symbol constellation corresponding to in-phase (I) (xr(nT)) and quadrature (Q) (jxi(nT)) phase components while also performing forward error correction (FEC) for later decoding when the signal is demodulated. The converter outputs are coupled to a QAM modulator 17 comprising identical finite impulse response (FIR) square-root raised Nyquist matched filters 25, 27. The Nyquist filters 25, 27 are a pair of identical interpolating low-pass filters which receive the I (xr(nT)) and Q (jxi(nT)) signals from the encoder 23 and generate real and imaginary parts of the complex band-limited baseband signal. The Nyquist filters 25, 27 ameliorate intersymbol interference (ISI) which is a by-product of the amplitude modulation with limited bandwidth. After filtering, the in-phase (Yr(nTxe2x80x2))and quadrature (jyinTxe2x80x2))components are modulated with mixers 29, 31 with the IF center frequencies 33, 35 and then summed 37 producing a band limited IF QAM output signal (g(nT)) for conversion 39 to analog 41 and transmitted.
A 40-tap matched Nyquist filter would require forty (40) binary multipliers which would consume substantial silicon area and adversely affect the maximum processing speed due to the multiply and accumulate operations (MAC). A multiplier implemented in digital form is inefficient and expensive due to logic gate count. Binary adders are less costly than binary multipliers, however, their use should also be minimized. To implement a design using binary multiplication and addition into an ASIC (application specific integrated circuit) would be expensive to manufacture and result in a more inefficient and slower signal throughput. Likewise, the same applies if programming a FPGA (field programmable gate array). Therefore, one disadvantage of FIR filters is the computational complexity required for each output sample. A QAM modulator constructed according to the teachings of the prior art may require separate integrated circuits rather than total integration onto an economical ASIC or FPGA.
Accordingly, there exists a need for a QAM modulator that increases computational throughput using one filter in conjunction with post filter carrier combination to reduce numeric operations while increasing speed.
The efficient quadrature amplitude modulator of the present invention allows a plurality of independent, compressed channels to occupy a 6 MHz bandwidth while reducing processing power by 33 percent for 8 levels of modulation offered by 64-QAM and by 25 percent for 16 levels of modulation offered by 256-QAM. The modulator achieves this efficiency using an improved digital filter architecture combining the modulation and filtering with post filtering carrier combination.
The QAM modulator presented is implemented with a reduction in the total number of binary parallel multipliers. To increase operational throughput, the speed of operation increases with the use of LUTs (look-up tables) storing precomputed filter weighting coefficients. The reduction in multipliers is also achieved by using post filtering carrier combination which similarly reduces the number of MAC operations performed during filtering. The invention can be construction either as a FPGA or an ASIC. The use of LUTs save significant chip resources and manufacturing cost.
Accordingly, the object of the present invention is to provide an efficient QAM modulator for multichannel applications.
It is a further object of the invention to provide a multichannel QAM architecture of reduced complexity and increased performance.
Other objects and advantages of this system will become apparent to those skilled in the art after reading the detailed description of the preferred embodiment.